Testing integrated circuits using few test probes

ABSTRACT

A method of testing integrated circuits, including establishing at least a first physical communication channel between a test equipment and an integrated circuit under test by having at least a first probe of the test equipment contacting a corresponding physical contact terminal of the integrated circuit under test; having the test equipment and the integrated circuit under test exchange, over said first physical communication channel, at least two signals selected from the group including at least two test stimuli and at least two test response signals, wherein said at least two signals are exchanged by means of at least one modulated carrier wave modulated by the at least two signals.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a division of U.S. patent application Ser. No.12/398,148, filed on Mar. 4, 2009, and also a continuation of U.S.patent application Ser. No. 12/982,753, filed Dec. 30, 2010, whichapplications claim the priority benefit of Italian patent applicationnumber MI2008A00365, filed on Mar. 5, 2008, which applications arehereby incorporated by reference to the maximum extent allowable by law.

BACKGROUND

1. Technical Field

The present invention relates to the field of Integrated Circuits (ICs),and particularly to methods and systems for IC testing.

2. Discussion of the Related Art

ICs are typically manufactured many at a time in the form of dies on asemiconductor material wafer. After manufacturing, the semiconductorwafer is diced, so as to obtain a plurality of individual IC chips.

Before being packaged and shipped to the customers, and installed invarious electronic systems, the individual ICs need to be tested forassessing their functionality, and in particular for ensuring that theyare not defective, that they respect prescribed specifications, and thatthey work properly. In particular, during the test, informationregarding global or local physical faults (such as the presence ofundesired short circuits and break-down events) of the IC integrated oneach die are obtained, and, more generally, the proper operation thereofis detected (for example, by checking the waveform of one or more outputsignals of the IC in response to predetermined stimuli). Only those dieswith ICs that meet predetermined requirements can proceed to thesubsequent manufacturing phases (such as wire bonding, packaging andfinal testing).

According to a known testing technique, the IC dies are tested beforethe semiconductor wafer is diced into the individual chips. The testconducted at the wafer level is referred to as “wafer sort” or“Electrical Wafer Sort” (“EWS”).

For example, in case of non-volatile semiconductor memory devices (suchas Flash memories) the EWS test is performed on each die on which thememory device is integrated, in order to assess the correct operationthereof, e.g. to detect possible defective memory cells.

For performing the test, a tester is used which is coupled to thesemiconductor wafer containing the IC dies to be tested, by means of aprobe card which is used for interfacing the semiconductor wafer to thetester.

The tester is adapted to manage signals that are employed for performingthe test. Hereinafter, such signals will be referred to as “testsignals” and are intended to include test stimuli (e.g., commands,addresses of memory locations of the memory device to be accessed inread or write, data to be written into the memory device) which aregenerated by the tester and which are sent, by means of the probe card,to each die to be tested, and test response signals (e.g., data readfrom the memory device) which are generated by the ICs integrated oneach die under test in response to the received test stimuli. The testresponse signals are sent by the IC integrated on each die under test tothe tester, which processes them to derive an indication of the properor improper operation of the ICs in the dies under test.

Often (for example during the EWS), the electrical coupling of the probecard with the ICs on the dies to be tested, necessary for achieving thesignals exchange, is accomplished through probes adapted to establish aphysical (mechanical and electrical) contact with corresponding contactpads on the ICs. For this purpose, the probe card consists of a PCB(Printed Circuit Board), which is connected to a large number (even ofthe order of some thousands) of mechanical probes, which are adapted tophysically contact input/output contact pads of each die to be tested.

However, this type of test system has several limitations.

For example, there is the risk of damaging the contact pads of the diesunder test. As known, a contact pad consists of an enlargedmetallization region of the IC; when the tip of the mechanical probestouches the pads, there is always the risk that one or more of the padsare damaged by scrubbing, and the likelihood that this happens increaseswith the number of probes.

Also, the parallel-testing capability is relatively low: indeed, whenseveral dies at a time have to be tested, the number of mechanicalprobes significantly increases; fabricating probe cards with many probesis not an easy task, and the finite dimensions of the probes pose aphysical limit to the density of probes per unit area.

Moreover, the higher the number of probes required, the more probable itis that the electrical contacts between the pads of the ICs under testand the mechanical probes are not good, and electrical discontinuitiesmay take place, which affect the test results.

Furthermore, when the contact pads are very close to each other (asituation frequently encountered due to the constant increase inintegration scale and size shrinking), it is very difficult to ensure agood physical contact of the mechanical probes with the contact pads.Such a problem is emphasized when the pads are small in size and/or alarge number thereof is present on each die.

In addition, the mechanical probes are very expensive, thus producingprobe cards with several probes negatively contributes to the increaseof the overall cost of the test system, and eventually of the ICs.

SUMMARY

The Applicant has tackled the problem of overcoming these and otherproblems.

The Applicant has found that a way to reduce the number of probesnecessary to perform the test of an IC is to employ a mixing of multipletest stimuli and/or test response signals over a same physicalcommunication channel between the probe card and an IC under test.

For example, according to an embodiment of the present invention, afrequency-division multiplexing scheme of the test signals isexpediently exploited for reducing the number of input/output contactpads which to be contacted by probes during the testing of the ICs onthe semiconductor wafer; in other words, in an embodiment of the presentinvention, signal carrier waves modulated at different operativefrequencies may be used for sending to the ICs multiple test stimuliover a same, first communication channel, and for sending back to thetester multiple test response signals over a same, first or secondcommunication channel, possibly coinciding with the first communicationchannel, thereby reducing the number of input/output contact pads whichare used during the testing of the dies on the semiconductor wafer. Forexample, by exploiting different frequencies for different test stimulito be fed to the IC under test, and/or for different test responsesignals generated by the IC (e.g., one frequency for a test stimulus,and another, different frequency for a test response signal), two ormore test stimuli and test response signals can be exchanged using asame probe.

According to an aspect of the present invention, a method of testingintegrated circuits is provided, comprising:

establishing at least a first physical communication channel between atest equipment and an integrated circuit under test by having a firstprobe of the test equipment contacting a corresponding physical contactterminal of the integrated circuit under test;

having the test equipment and the integrated circuit under testexchange, over said first physical communication channel, at least twosignals selected from the group consisting of at least two test stimuliand at least two test response signal,

wherein said at least two signals are exchanged by means of at least onemodulated carrier wave modulated by the at least two signals.

According to another aspect of the present invention, a test equipmentfor testing integrated circuits is provided, comprising:

at least one first probe adapted to contact a corresponding physicalcontact terminal of an integrated circuit under test for establishing atleast a first physical communication channel between the test equipmentand the integrated circuit under test;

means for exchanging with the integrated circuit under test, over saidfirst physical communication channel, at least two signals selected fromthe group consisting of at least two test stimuli and at least two testresponse signal,

wherein said at least two signals are exchanged by means of at least onemodulated carrier wave modulated by the at least two signals.

According to still another aspect of the present invention, anintegrated circuit is provided, comprising:

at least one integrated circuit core;

at least one externally-accessible terminal, adapted to be contacted byat least a probe of a test equipment for testing the integrated circuitcore, so as to establish at least a first physical communication channelbetween the test equipment and the integrated circuit;

means for performing a test based on test stimuli received from the testequipment; and

means for exchanging with the test equipment, over said first physicalcommunication channel, at least two signals selected from the groupconsisting of at least two test stimuli generated by the test equipmentand at least two test response signals generated by said means forperforming a test,

wherein said at least two signals are exchanged by means of at least onemodulated carrier wave modulated by the at least two signals.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other features and advantages of the present invention will bemade apparent by the following detailed description of an embodimentthereof, provided merely by way of non-limitative example, descriptionthat will be conducted making reference to the attached drawings,wherein:

FIG. 1 schematically shows a block diagram of a test system according toan embodiment of the present invention;

FIG. 2 schematically shows a portion of the test system of FIG. 1according to an embodiment of the present invention;

FIG. 3 schematically shows a portion of the test system of FIG. 1according to another embodiment of the present invention;

FIG. 4 schematically shows a portion of the test system of FIG. 1according to still another embodiment of the present invention;

FIGS. 5A and 5B schematically show cross-sectional views of a probe cardaccording to an embodiment of the present invention, adapted to be usedin the test system of FIG. 1;

FIGS. 6A and 6B partially show cross-sectional views of a probe cardaccording to an embodiment of the present invention;

FIGS. 7A and 7B partially show cross-sectional views of a probe cardaccording to another embodiment of the present invention;

FIGS. 8A and 8B partially show cross-sectional views of a probe cardaccording to still another embodiment of the present invention; and

FIGS. 9A-9D schematically show in terms of very simplified functionalblocks a 3D IC structure according to various embodiments of the presentinvention.

DETAILED DESCRIPTION

Throughout the following description, identical or similar elements inthe drawings are denoted by same reference numerals.

Referring to FIG. 1, a block diagram of a test system 100 according toan embodiment of the present invention is schematically shown. The testsystem 100 is adapted to perform the wafer-level testing of a plurality(for example, hundreds) of IC dies 105 belonging to a semiconductorwafer 110, prior to the dicing thereof into individual chips.

The specific type of IC 115 integrated on the dies 105 is not limitativeto the present invention; in particular, and merely by way of example,the ICs 115 may be or include memory devices, microprocessors ormicrocontrollers, Digital Signal Processors (DSPs), digital logiccircuits, Application Specific Integrated Circuits (ASICs), FieldProgrammable Gate arrays (FPGAs), analog circuits, RF circuits, MEMS(Micro Electro Mechanical Systems).

For testing the ICs 115 on the dies 105 in order to assess theirfunctionality, the test system 100 comprises a tester 120, which is anequipment adapted to manage test signals, and in particular to generatetest stimuli to be fed to the ICs 115 integrated on the dies 105, and toprocess test response signals received from the ICs 115 under test; thetester 120 is coupled to a probe card 125, which is adapted tocommunicate with the tester 120 through wire line and/or wirelesselectrical signal distribution means 130 (which may be or includeelectrical cables, conductive lines or tracks, a wireless radio link oran optical link); in particular, the probe card 125 is adapted toexchange the test signals with the tester, and receives from the testerthe power supply necessary for its operation; the probe card 125 isemployed for interfacing the tester 120 with the IC 115 on each die 105on the wafer 110.

The probe card 125 comprises a control circuit 135 adapted to manage thetest signals exchanged with the tester 120, and a testing section 137comprising a plurality of communication units 140, each of which isadapted to communicate with a corresponding communication unit 145provided in each die 105 of the wafer under test. In other words, eachof the communication units 140 of the testing section 137 of the probecard 125 is adapted to establish in use a one-to-one communicationrelationship with a corresponding communication unit 145 provided on acorresponding one of the dies 105 of the semiconductor wafer 110 to betested. It is pointed out that, in some embodiments of the invention,the plurality of communication units 140 of the probe card 125 mayinclude a number of units 140 equal to the number of dies 105 of thewafer 110 to be tested (in which case, all the dies of the wafer can inprinciple be tested in parallel); however, in alternative inventionembodiments, the number of communication units 140 of the probe card 125may be lower than the number of dies 105 of the wafer 110 (in whichcase, groups of dies of the wafer are tested in parallel, and, in orderto test the full wafer, the probe card can be sequentially displaced bypredetermined steps with respect to the wafer under test, or acommunication unit 140 can test more than one die 105), or the number ofcommunication units 140 of the probe card may be even greater than thenumber of dies 105 of the specific wafer under test (in which case, onlya subset of the probe card communication units 140 are used for testingthe whole wafer, or one die 105 can be tested by means of more than onecommunication unit 140).

The tester 120 and the control circuit 135 of the probe card 125 maycommunicate through a tester interface input/output circuit 150. Thecontrol circuit 135 comprises for example data/signal processors 155which control the overall operation of the probe card 125, and whichoperates under the control of a software/firmware stored in localstorage units 160.

Each communication unit 140 includes at least onetransponder/transceiver 165 (that can comprise coding/decodingcircuits), which is coupled to at least one filter unit 170. A DeviceUnder Test (DUT) interface unit 175 is provided for each communicationunit 140, for the coupling with a respective die of the wafer undertest; more in detail, the DUT interface unit 175 comprises a pluralityof probes (for example, of MEMS type, or cantilever probes or verticalprobes) which are used for establishing a physical communication channelwith the corresponding communication unit 145 provided on the die 105.

Similarly, each communication unit 145 on the die 105 includes at leastone transponder/transceiver 180 (that, similarly to thetransponder/transceiver 165, can comprise coding/decoding circuits),which is coupled to at least one further filter unit 185 and to a probecard interface unit 190 comprising a plurality of input/output contactpads, which are used for being contacted by the probes belonging to thecorresponding DUT interface unit 175. A Built In Self Testing (BIST)circuitry 195 may be provided on the die 105, adapted to coupling thecommunication unit 145 with the core integrated circuit 115 and toperform the testing of the IC.

The transponder/transceiver 165, with the associated filter unit 170 andthe DUT interface unit 175, and the transponder/transceiver 180, withthe associated filter unit 185 and probe card interface unit 190, areadapted to establish a bi-directional communication link between theprobe card 125 and a corresponding die 105 of the wafer under test 110.

During the testing, the generic transponder/transceiver 165 on the probecard 125 encodes the test stimuli received from the tester 120 andtransmits them to the transponder/transceiver 180 on the respective die105 of the wafer, using any suitable coding and modulation schemes.Examples of modulation schemes include Amplitude Modulation (AM),Frequency Modulation (FM), Pulse Code Modulation (PCM), Phase Modulation(PM) or any combination thereof. The specific coding and modulationschemes are not per-se limitative of the present invention.

Then, the transponder/transceiver 180 receives, demodulates and decodesthe test stimuli, provides the demodulated and decoded test stimuli tothe BIST circuitry 195, and the test stimuli are then used by the BISTcircuitry 195 for testing the IC 115 integrated on the die 105. Testresponse signals are generated by the IC 115 in response to theperformed test: the test response signals are then encoded, modulatedand transmitted by the transponder/transceiver 180 to the probe card125, where the transponder/transceiver 165 performs a demodulation anddecoding of the received signals, and the test response signals are thensent to the tester 120, which processes them to assess the functionalityof the IC 115 integrated on the die 105 under test.

In the example at issue, as better described in the following, the powersupply necessary for the operation of the ICs 115 under test is suppliedthereto by means of the probes belonging to each DUT interface unit 175.

In particular, according to an embodiment of the present invention, inorder to reduce the number of input/output contact pads used for testingthe ICs on the dies 105 of semiconductor wafer 110, the test signals areexchanged through a reduced number of physical communication channels(each comprising the DUT interface 175 and the probe card interface190). For this purpose, a signal mixing, based on a suitable coding andmodulation scheme of the test signals, for example a frequency divisionmultiplexing scheme, is used. As better shown in FIG. 2, thetransponder/transceiver 165 for example encodes and modulates the teststimuli received from the tester 120 and transmits them with a firstmodulation frequency f1 (for example, ranging from 30 Hz to 300 GHZ,e.g. 30 KHz), whereas the test response signals generated by the IC 115under test are encoded, modulated and transmitted by thetransponder/transceiver 180 to the probe card 125 with a secondmodulation frequency f2 (for example, ranging from 30 Hz to 300 GHZ,e.g. 50 KHz) which is different from the first frequency f1. In otherwords, according to an embodiment of the present invention, bydifferentiating the radio frequencies used for transmitting the teststimuli and the test response signals, it is possible to use only onephysical communication channel for the exchange of the test signalsbetween the probe card 125 and the wafer 110.

Referring to FIG. 2, an exemplary implementation of the unit 140 and thecommunication unit 145 is shown.

The unit 140 receives from the tester interface input/output circuit 150(not shown in FIG. 2) a reference voltage GND through a referencevoltage distribution line 205, a supply voltage VCC through a supplyvoltage distribution line 210, and the test signals through a testsignals distribution line 215. The test signals distribution line 215 isconnected to an input terminal 220 of the transponder/transceiver 165.

The supply voltage distribution line 210 and the reference voltagedistribution line 205 respectively feed the supply voltage VCC and thereference voltage GND to a first probe 225 and a second probe 230 of theDUT interface unit 175. For this purpose, the first probe 225 has afirst input terminal 235, which is connected to the supply voltagedistribution line 210. Similarly, the second probe 230 has a secondinput terminal 240, which is connected to the reference voltagedistribution line 205. Moreover, the first probe 225 and the secondprobe 230 have respectively a first output terminal or tip 245 and asecond output terminal or tip 250, which are adapted to contact thecorresponding die 105 under test, and particularly the respective probecard interface unit 190 on the die 105.

In the example at issue, the filter unit 170 comprises a first capacitorC0 having a first terminal 255 connected to the first probe 225 and asecond terminal 260 connected to an output terminal 265 of thetransponder 165.

The probe card interface unit 190 which is provided in the communicationunit 145 of the die 105 includes a first input/output contact pad 270and a second input/output contact pad 275 which are adapted to becontacted during the test of the die 105 by the tips 245 and 250 of thefirst probe 225 and the second probe 230, respectively. The input/outputcontact pad 270 is connected to an input terminal 280 of the filter unit185, whereas the contact pad 275 is connected to an input terminal 281of the transponder/transceiver 180 (so that the pad 275 provides thereference voltage GND to the transponder 180).

In the example at issue, the filter unit 185 comprises a second and athird capacitors C1 and C2 and an inductor L0. More in detail, theinductor L0 has a first terminal INL0, which is connected to the filterunit input terminal 280, and a second terminal OUTL0, which is connectedto a first terminal INC2 of the capacitor C2. A second terminal OUTC2 ofthe capacitor C2 is kept to the reference voltage GND. Moreover, thefirst terminal INC2 of the capacitor C2 is connected to a first outputterminal 285 of the filter unit 185.

In turn, the capacitor C1 has a first terminal INC1, which is connectedto the input terminal 280, and a second terminal OUTC1, which isconnected to a second output terminal 290 of the filter unit 185. Thefirst output terminal 285 and the second output terminal 290 areconnected to the transponder/transceiver 180.

During the testing, the reference voltage GND and the supply voltage VCC(which are essentially constant, time-invariable voltages, or vary atvery low frequencies) are fed to the communication unit 145. Inparticular, the second probe 230, by directly contacting theinput/output contact pad 275, provides the reference voltage GND to thetransponder/transceiver 180. Similarly, the supply voltage VCC is fed tothe communication unit 145 by means of the first probe 225, which isadapted to directly contact the input/output contact pad 270. The supplyvoltage VCC does not affect the voltage reached by the output terminal265, since the first capacitor C0 has a high impedance (ideally, it isan open circuit) at low frequencies. Through the probe 225 and thecontact pad 270, the IC on the die under test 105 receives a signalbeing the superposition of an essentially DC (Direct Current) signal,corresponding to the supply voltage VCC, and of the test stimuli,encoded and modulated at the first frequency f1. This combined signal isfed to the filter 185, which separates the DC component from the signalcomponent at the first frequency f1. The DC component, corresponding tothe supply voltage VCC, is made available at the first output terminal285 of the filter 185, and is fed to the transponder/transceiver 180,since the inductor L0 has a low impedance (ideally, it behaves as ashort circuit in DC). The second capacitor C2 does not affect thevoltage reached by the first output terminal 285 since it has a highimpedance (ideally, it behaves as an open circuit in DC). In DC, alsothe capacitor C1 has a high impedance (ideally, it behaves as an opencircuit), thus the DC signal component does not reach the second outputterminal 290 of the filter 185.

The signal component at the first radio frequency f1 is made availableat the second output terminal 290 of the filter 185, and is sent to thetransponder/transceiver 180, since the capacitor C1, at the firstfrequency f1, has a low impedance (ideally, it behaves as a shortcircuit). The signal component at the first frequency f1 does not reachthe first output terminal 285 of the filter 185, since at the firstfrequency f1 the capacitor C2 has a low impedance (ideally, it behavesas a short circuit), and the inductor L0 has a high impendence (ideally,it behaves as an open circuit); thus, the signal carrying the teststimuli do not affect the voltage at the first output terminal 285 ofthe filter unit 185. In this way, the essentially DC component (carryingthe voltage supply) and the component at the first frequency f1(carrying the test stimuli) of the combined signal transmitted to thedie 105 through the probe 245 are effectively separated by the filter185

The transponder/transceiver 180 receives, demodulates and decodes thetest stimuli, and the test stimuli are then supplied to the BISTcircuitry 195 for testing the IC 115 integrated on the die 105; testresponse signals are generated in response to the test performed by theIC 115 based on the received test stimuli: the test response signals areencoded, modulated and transmitted with the second radio frequency f2 bythe transponder/transceiver 180 to the probe card 125 over the samecommunication channel formed by the contact pad 270 and the probe 225.The transponder/transceiver 165 performs a demodulation and decoding ofthe received, modulated and coded test response signals, and thedemodulated and decoded test response signals are then sent (in a waysimilar to that described above) to the tester 120, which processes themto assess the functionality of the IC 115 integrated on the die 105under test.

In this way, in the exemplary invention embodiment being described, onlytwo input/output contact pads need to be contacted by probes for testingthe IC on the die 105, since the test stimuli and the test responsesignals are exchanged with different operative radio frequenciesexploiting a same physical communication channel, i.e. a same probe.

In FIG. 3 an exemplary implementation of the unit 140 and thecommunication unit 145 according to another embodiment of the presentinvention is shown. In this case, three physical communication channels,comprising three probes and corresponding contact pads on the die undertest are used for communicating with the generic IC 115 under test. Thesupply voltage distribution line 210 on the probe card is coupled to athird probe 305 (an additional probe compared to the two probes 225 and230 of the previous embodiment) which is adapted for contacting acorresponding input/output contact pad 310 of the probe card interfaceunit 190. In this case, the supply voltage VCC reaches directly thetransponder/transceiver 180. The filter unit 185 does not have toperform a separation of signal components at DC and at the firstfrequency, thus it can be simplified. In particular, the filter unit 185may eventually comprise only the capacitor C1 (C2 can be omitted);alternatively, both the capacitors C0 and C1 may be omitted. However,the presence of optimized filters 170, 185 becomes particularly usefulwhen the frequencies used for modulating the test signals are so highthat the physical communication channels need to be characterized bymeans of a distributed-parameters electrical model.

In FIG. 4, an exemplary implementation of the unit 140 and thecommunication unit 145 according to still another embodiment of thepresent invention is shown. In this case, compared to the embodiment ofFIG. 3, a still additional physical communication channel 405 isprovided, comprising a distribution line 410 on the probe card, which isconnected to a fourth probe 415. The probe 415 is adapted to contact acorresponding input/output contact pad 420 of the probe card interfaceunit 190. Through the additional channel 405, additional test signalscan be exchanged; for example, the additional channel 405 may beexploited for testing the integrated circuit 105 without the use of theBIST circuit 195. For example, the additional channel can be employedfor testing power circuits or RF circuits or analog circuits or forAutomatic Tester Equipment (ATE) essential resources use in order tomeasure particular parameters or characteristics.

In the following, exemplary embodiments of the probe card are presented,adapted to be used in the context of the present invention.

Referring to FIGS. 5A and 5B, a cross-sectional view of a test equipment500 is schematically shown, in which an exemplary structure and thepositioning of the probe card 125 according to an embodiment of thepresent invention and the semiconductor wafer 110 to be tested isvisible.

The semiconductor wafer 110 to be tested is placed on a chuck 505, whichis capable of movement in the three orthogonal directions “x”, “y” and“z” schematically indicated in the drawing. The chuck 505 may also berotated and tilted, and it may be further capable of other movements, sothat once the semiconductor wafer 110 is placed on the chuck 505, thelatter is moved in order to bring the dies 105 of the wafer 110 to betested close to the probe card 125, for enabling the communicationtherewith.

In the example at issue, the probe card 125, in one of its embodiments,includes a PCB 510 forming a support for a pseudo wafer 515, comprisinga plurality of dies, each one forming an elementary probe unit 520.

The PCB 510 comprises all the circuitry, which is employed for thecommunication between the tester (not shown in figures) and thesemiconductor wafer 110 under test. For example, the PCB 510 comprisesthe tester interface input/output unit 150, the data/signal processors155, and the storage units 160.

A top view of the probe card 125 (including the pseudo wafer 515) andthe semiconductor wafer 110 is also schematically shown in the drawing.

As visible, the elementary units 520 are arranged in the pseudo siliconwafer 515 in order to form a two-dimensional arrangement, whichcorresponds, to the arrangement of dies on the semiconductor wafer 110under test. In particular, the pseudo wafer 515 comprises an array ofthe elementary units 520 which reproduce a shape of the wafer to betested. In an embodiment of the present invention, each of theelementary unit 520 of the pseudo 515 belonging to the probe card 125 isadapted to establish a one-to-one communication relationship with acorresponding die of the semiconductor wafer 110 to be tested, a numberof MEMS probes adapted to contact the pads of an IC. It is to beappreciated that probes of different type or arranged with a differentarchitecture can be used (e.g. vertical probes, or pogo pins).

In particular, as better described in the following, each elementaryunit 520 may be formed starting from a silicon die, individually dicedand finally assembled with the other elementary units 520 in order toform the pseudo wafer 515 having a shape corresponding to thesemiconductor wafer 110 to be tested.

Referring to FIGS. 6A and 6B, a portion of the probe card 125 accordingto an embodiment of the present invention is shown. In particular, FIGS.6A and 6B show an elementary unit 520 according to an embodiment of thepresent invention. The elementary unit 520 includes a silicon die 605which is connected, e.g. by chip on board/flip-chip techniques, to thePCB 510. In particular, bumps 610 are provided in order to connect a topsurface 615 of the silicon die 605 to the PCB 510. A complex conductivepath (not completely shown in the figures) that can include one or moreconductive through vias 620, particularly Through Silicon Vias (TSVs),is provided crossing the silicon die 605 in order to connect the topsurface 615 to a bottom surface 625 of the silicon die 605. Mechanicalelements forming probes 630 (one of which is shown in FIG. 6B),particularly of MEMS type, are connected to the bottom surface 625 ofthe silicon die 605. In particular, the through vias 620 are adapted toelectrically connect the MEMS probes 630 to the top surface 615 of thesilicon die 605 and thus to the PCB 510, through a conductive path (onlypartially shown in the drawing).

The transponders/transceivers 165 are integrated in the silicon die 605.

In particular, for electrically contacting the input/output contact padsof the die to be tested and exchanging the test signals between theinput/output contact pads and the tester (not shown in figure), the PCB510 has corresponding conductive paths 635 which electrically couple thetester to the silicon die 605 and thus to the probes 630. In particular,for testing the ICs of the wafer dies in order to assess theirfunctionality, the tester is adapted to generate test stimuli to be fedto the ICs integrated on the dies belonging to the semiconductor wafer110; the tester is coupled by means of the PCB 510 to the elementaryunits 520, each one of which is adapted to be fed by the tester throughthe conductive paths 635 with the test stimuli, and the power supplynecessary for its operation.

In other words, the MEMS probes 630, the through vias 620, the bumps 610and the conductive paths 635, are adapted to establish a bi-directionallink between the tester and each die of the semiconductor wafer 110under test (or groups of dies).

In an embodiment of the present invention, the probe card 125 receivesthe test stimuli from the tester, encodes, modulates and transmits themwith the first radio frequency f1 to the ICs on the dies to be testedusing the MEMS probes 630. The test stimuli, after having beendemodulated and decoded, are then used to test the IC integrated on thedie belonging to the semiconductor wafer 110; test response signals aregenerated by the ICs in response to the test stimuli. The test responsesignals are encoded, modulated and transmitted at the second radiofrequency f2 to the probe card 125, and then, after having beendemodulated and decoded, they are sent to the tester, which processesthem to assess the functionality of the IC integrated on the die undertest.

Referring to FIGS. 7A and 7B, an elementary unit 520 according toanother embodiment of the present invention is shown. Similarly to thepreceding case, each elementary unit 520 comprises the silicon die 605,bumps 610, through vias 620 and the MEMS probe 630. In this case thetransponder/transceiver 165 is integrated in an auxiliary die 710 whichis connected, e.g. by chip on board/flip-chip techniques, to the PCB510. In particular, bumps 715 are provided in order to connect a bottomsurface 720 of the auxiliary die 710 to the PCB 510 and/or for theconnection to the tester.

Moreover, for electrically contacting the input/output contact pads ofthe die to be tested and exchanging the test signals between theinput/output contact pads and the tester (not shown in figures), the PCB510 has corresponding conductive paths 725 which electrically couple thebumps 610 to the bumps 715 so as to couple the tester to the silicon die605 and thus to the probes 630.

Further conductive paths 730 are provided for electrically coupling thetransponder 165 to the circuits belonging to the PCB 510.

Referring to FIGS. 8A and 8B, an elementary unit 520 according to stillanother embodiment of the present invention is shown.

With respect to the preceding embodiment, the silicon die 605 issubstituted by a ceramic layer 805 to which the probes 630 areconnected. In particular, the ceramic layer 805 is employed for forminga support for the probes 630. Conductive paths 810 are provided withinthe ceramic layer 805 for electrically coupling each probe 630 to thecorresponding conductive path 725.

The present invention allows testing the ICs integrated on the dies ofthe semiconductor wafer 110 by using a reduced, possibly very low numberof contact pads and probes, thereby improving the performance and thereliability of the testing, and reducing the costs of the testequipment.

Although in the preceding description reference has been made to a testsystem wherein each communication unit 145 in the dies to be testedincludes only one transponder/transceiver, two or moretransponders/transceivers can be provided in each communication unit145. In such a way, according to an embodiment of the present invention,each transponder/transceiver may be used not only for performing thetesting, but also for other applications. For example, thetransponders/transceiver integrated in each communication unit may beused for chip-to-chip communication in multi-chip systems (such asSystems In Package—SIPs), or, in case the dies integrateSystems-on-Chip, made up of several different functional units (e.g.,CPU, memory, input/output buffers), for the communication between thedifferent units within the IC. In particular, the communication unit 145provided in each die 110 may be exploited, when the dies containingdifferent ICs are packaged in a single package to form a SIP, for thecommunication between the different ICs of the SIP, thereby reducing thenumber of signal lines necessary for their interconnection. Similarly,in the case of a SoC, the communication between the different functionalunits thereof may take advantage of the presence of the communicationunit 145, thereby the number of signal lines to be formed on the IC maybe greatly reduced.

According to an embodiment of the present invention, multiple teststimuli can be mixed and sent by the probe card to the generic IC undertest over a same communication channel, i.e. through one probe, byexploiting different frequencies. For example, considering the case ofICs formed of or including semiconductor memories, commands, addresssignals and input data can be sent to the memory IC through a same probeConventionally, address signals are supplied to the IC using severalprobes, contacting the multiplicity of address contact pads of thememory, and input data are supplied to the IC using several otherprobes, contacting the multiplicity of data contact pads of the memory.

According to a further embodiment of the present invention, using a sameprobe and contacting one pad only on the IC, the commands can be sentcoding and modulating them over a signal carrier at one frequency, theaddress signals can be sent coding and modulating them over a signalcarrier at another frequency, and the input data can be sent coding andmodulating them over a signal carrier at still another frequency.Properly designed filter units in the probe card and in the ICs may beused to separate the different signal components.

According to a still further embodiment of the present invention, afirst communication channel, i.e. one probe, can be used forcommunications from the probe card to the IC under test, to send to theIC under test multiple test stimuli, and a second communication channel,i.e. another probe, can be used for communications from the IC undertest back to the probe card, to send the multiple test response signals(for example, the output data of a memory device, generally comprised ofeight or sixteen bits, may be coded and modulated and sent through oneprobe only). Multiple test stimuli can be mixed and sent over the firstcommunication channel, and, similarly, multiple test response signalscan be mixed and sent over the second communication channel, for exampleadopting a frequency-division multiplexing scheme; the differentfrequencies used in the second communication channel for sending thetest response signals may be the same as those used in the firstcommunication channel for sending the test stimuli, since the twochannels are separated.

The concepts of the present invention can be advantageously applied toeven more complex IC structures, as in a three dimensional (3D) ICstructure. As it is well known to those skilled in the art, a 3D ICstructure is formed by a plurality of vertically stacked device layers,each one including at least one respective semiconductor chip. Thesemiconductor chip of a generic device layer may be physically linked tothe semiconductor chips of the adjacent device layers in the stack bymeans of a wafer bonding process; alternatively, starting from a bottomsemiconductor substrate, the semiconductor chips of the various devicelayers may be formed by means of an epitaxial growth process. With a 3DIC structure it is possible to integrate a relatively complex systemwithout having to waste an excessive silicon area. For example, thebottom device layer of a 3D IC structure may be directed to theintegration of processing and logic circuits, an intermediate devicelayer may be directed to the integration of memory circuits, and the topdevice layer may be directed to the integration of input/output circuitsand converters. A generic device layer is able to exchange signals andreference and supply voltages with the adjacent device layers in thestack by means of respective through vias, and particularly TSVs,vertically crossing the semiconductor chip of the device layer from thetop surface to the bottom surface thereof. With an arrangement of suchtype, a 3D IC structure is able to receive and provide signals andreference and supply voltages from/to the outside through input/outputcircuits and contact pads which are integrated for example on the topsurface of the top device layer only. Indeed, the lower device layerscannot be directly accessed, lacking of free surfaces provided withcontact pads that can be reached from the outside. This drawbacknegatively affects the test operations to be performed on a 3D ICstructure, since a probe card cannot directly interface the tester withthe integrated circuits corresponding to the lower device layers. Theonly way the test signals provided by the probe card are able to reachthe integrated circuits of a generic lower device level is throughphysical communication channels that cross the semiconductor chips ofthe higher device levels. As a consequence, since all the test signalsneeded for assessing the functionality of the whole 3D IC structure haveto pass through the top device level, the number of probes of the probecard that have to be coupled to contact pads on the top surface of saiddevice level during the test operations becomes really high. For thereasons already described, a probe card requiring a too high number ofprobes is not efficient, and is very expensive.

According to an embodiment of the present invention, the proposedsolution of reducing the number of probes necessary to perform the testoperations by employing a mixing of multiple test stimuli and/or testresponse signals over a same physical communication channel can beadvantageously exploited for overcoming the abovementioned problems.

Referring to FIG. 9A, an exemplary 3D IC structure 904 according to anembodiment of the present invention is shown in terms of very simplifiedfunctional blocks. For the sake of simplicity, the exemplary 3D ICstructure 904 is partitioned in two device levels only—referred to astop device level and bottom device level—, but the concepts of thepresent invention can be applied to any number of device levels.

The top device level includes a semiconductor chip 906 having a top mainsurface 908 and a bottom main surface 910; the semiconductor chip 906integrates a first integrated circuit, globally identified with thereference ICA. Similarly, the bottom device level includes asemiconductor chip 912 having a top main surface 914 and a bottom mainsurface 916; the semiconductor chip 912 integrates a second integratedcircuit, identified with the reference ICB.

The semiconductor chips 906 and 912 forming the 3D IC structure 904 arearranged in a vertical stack, with the bottom main surface 910 of thesemiconductor chip 906 that overtops the top main surface 914 of thesemiconductor chip 912.

For allowing the integrated circuit ICA to be electrically supplied fromthe outside of the 3D IC structure 904 during its operation, thesemiconductor chip 906 is provided with a dedicated first supply bus918. More in detail, the first supply bus 918 includes a supply voltageline 920 coupling the integrated circuit ICA with a respective contactpad 921 on the top main surface 908; the first supply bus 918 furtherincludes a reference voltage line 922 coupling the integrated circuitICA with another respective contact pad 923 on the top main surface 908.In this way, the integrated circuit ICA can be fed from the outside ofthe 3D IC structure 904 with a supply voltage VCCA (through the contactpad 921 and the supply voltage line 920) and a reference voltage GNDA(through the contact pad 923 and the reference voltage line 922).

Similarly, in order to exchange input/output signals (such as command,data and address signals) with the outside of the 3D IC structure 904, afirst operative bus 924 couples the integrated circuit ICA with a set ofrespective contact pads on the top main surface 908, globally indicatedin the figure with the reference 925.

For electrically supplying the integrated circuit ICB, a second supplybus 926 is provided, which vertically crosses the semiconductor chip 906from the top surface 908 to the bottom surface 910 thereof (e.g., bymeans of respective TSVs) for reaching the top surface 914 of thesemiconductor chip 912, and then the integrated circuit ICB.

More in detail, the second supply bus 926 includes a reference voltageline 927 coupling the integrated circuit ICB with a respective contactpad 928 on the top main surface 908 of the semiconductor chip 906; thesecond supply bus 926 further includes a supply voltage line 929coupling the integrated circuit ICB with a further respective contactpad 930 on the top main surface 908 of the semiconductor chip 906. Theintegrated circuit ICB can be fed from the outside of the 3D ICstructure 904 with a reference voltage GNDB (through the contact pad 928and the reference voltage line 927) and a supply voltage VCCB (throughthe contact pad 930 and the supply voltage line 929).

In order to exchange command, data and address signals with the outsideof the 3D IC structure 904, the integrated circuit ICB is coupled withthe semiconductor chip 906 through a second operative bus 931. By meansof respective TSVs, the second operative bus 931 reaches the integratedcircuit ICA, in such a way that the signals carried by said operativebus 931 may be provided/received to/from the outside of the 3D ICstructure 904 exploiting the first operative bus 924 and the respectivecontact pads 925 on the top main surface 908. In addition or inalternative, the second operative bus 931 may be also directly connectedwith the first operative bus 924.

In order to test its functionality, the 3D IC structure 904 ispositioned close to the probe card 125, for bringing the contact padslocated on the top surface 908 of the semiconductor chip 906 in contactwith the probes of the probe card 125, in such a way to enable thecommunication between the tester 120 and the integrated circuit ICA ofthe semiconductor chip 906. Particularly, during the test operations,the integrated circuit ICA is supplied by means of probes of the probecard 125, which physically contact the contact pads 921 and 923 forproviding the supply voltage VCCA and the reference voltage GNDA.Moreover, the test signals generated during the test operations areexchanged between the tester 120 and the integrated circuit ICA by meansof further probes of the probe card 125, which physically contact thecontact pads 925.

Similarly, during the test operations, the integrated circuit ICB issupplied by means of probes of the probe card 125 that physicallycontact the contact pads 928 and 930 for providing the supply voltageVCCB and the reference voltage GNDB.

During the testing, according to an embodiment of the present invention,the test stimuli generated by the tester 120 to be provided to theintegrated circuit ICB and the test response signals generated by thelatter circuit in response to the received test stimuli are exchangedbetween the probe card 125 and the integrated circuit ICB by means ofthe second supply bus 926, and particularly by encoding and transmittingthem over at least one among the lines forming the second supply bus926.

For this purpose, the semiconductor chip 912 is provided with acommunication unit 932 of the same type of the communication unit 145previously described. The communication unit 932 comprises at least onetransponder/transceiver 933 (comprising coding/decoding circuits)coupled with at least one filter unit 934. Particularly, according to anembodiment of the present invention, the filter unit 934 has an inputconnected to the supply voltage line 929, a first output connected tothe integrated circuit ICB, and a second output connected to an input ofthe transponder/transceiver 933. The transponder/transceiver 933 has anoutput coupled with the integrated circuit ICB by means of a thirdoperative bus 935.

In the same way as for the previous embodiments, the probe card 125encodes the test stimuli generated by the tester 120 and transmits themto the communication unit 932 by means of any suitable coding andmodulation scheme using a first modulation frequency fm1 (for example,ranging from 30 Hz to 300 GHZ). Particularly, the probe card 125superimposes the encoded and modulated test stimuli to the supplyvoltage VCCB (which is essentially constant) over the supply voltageline 929, providing it to the alter unit 934. The filter unit 934separates the DC component—which corresponds to the supply voltageVCCB—from the signal component at the first modulation frequencyfm1—which corresponds to the encoded and modulated test stimuli. Whilethe DC component is directly provided to the integrated circuit ICB forthe electric supply thereof, the signal component corresponding to theencoded and modulated test stimuli is demodulated and decoded by thetransponder/transceiver 933, which accordingly retrieves the teststimuli generated by the tester 120 and provides it to the integratedcircuit ICB by means of the third operative bus 935. The test responsesignals generated by the integrated circuit ICB in response to theperformed test are then encoded, modulated and transmitted by thetransponder/transceiver 933 to the probe card 125 over the supplyvoltage line 929, using a second modulation frequency fm2 different fromthe first modulation frequency.

In the same way as for the previous embodiments, a BIST circuitry may beprovided in the semiconductor chip 912, adapted to couple thecommunication unit 932 with the integrated circuit ICB and to performthe testing thereof (similar considerations apply to the testing of theintegrated circuit ICA).

Thus, with embodiments of the present invention, it is possible todrastically lower the number of probes necessary to perform the testingof the integrated circuits of a 3D IC structure, overcoming all theabovementioned drawbacks.

According to a further embodiment of the present invention illustratedin FIG. 9B, also the semiconductor chip 906 is provided with acommunication unit 936 coupled with the supply bus 918 in the same wayas the communication unit 932. As a consequence, the probe card 125 maysend test stimuli to the integrated circuit ICA and receive testresponse signal therefrom without having to physically access with theprobes dedicated contact pads on the top surface of the semiconductorchip 906. In this way, the number of probes required for performing thetest operations are further reduced.

According to a still further embodiment of the present inventionillustrated in FIG. 9C, the integrated circuits ICA and ICB of the 3D ICstructure 904 share a same supply bus 937. The supply bus 937 comprisesa supply voltage line 938 adapted to provide a same supply voltage VCCSand a reference voltage line 939 adapted to provide a same referencevoltage GNDS to both the integrated circuits ICA and ICB.

According to this embodiment of the present invention, the test stimuligenerated by the tester 120 to be provided to the integrated circuitsICA, ICB and the test response signals generated by the latter circuitsin response to the received test stimuli are exchanged between the probecard 125 and the integrated circuits by means of the supply bus 937, andparticularly by encoding and transmitting them over at least one amongthe lines forming the supply bus 937. Particularly, the test stimulidirected to the integrated circuit ICA are transmitted over the supplyvoltage line 938 using a first modulation frequency, while the teststimuli directed to the integrated circuit ICB are transmitted over thesame supply voltage line 938 using a second modulation frequencydifferent from the first one. In this case, both the semiconductor chips906 and 912 are provided with a respective communication unit 940, 941coupled with the supply voltage line 938. Particularly, thecommunication unit 940 integrated in the semiconductor chip 906 isadapted to collect the signal component at the first modulationfrequency from the supply voltage line 938, and perform demodulating anddecoding operations for retrieving the test stimuli for the integratedcircuit ICA. Moreover, the communication unit 941 integrated in thesemiconductor chip 912 is adapted to collect the signal component at thesecond modulation frequency from the supply voltage line 938, andperform demodulating and decoding operations for retrieving the teststimuli for the integrated circuit ICB.

The concepts of the present invention can be applied to further 3D ICstructure configurations, different from that illustrated in the FIGS.9A-9C.

For example, the integrated circuits ICA and ICB may share a samereference voltage line adapted to convey a reference voltage to be usedby both the integrated circuits, but each integrated circuit ICA, ICBmay be coupled with a respective supply voltage line adapted to convey adedicated supply voltage. In this case, by providing each semiconductorchip 906, 912 with a communication unit comprising atransponder/transceiver and a filter coupled with the respective supplyvoltage line, test stimuli and test response signals for both theintegrated circuits can be encoded and modulated for beingadvantageously transmitted over the supply voltage lines.

Moreover, even in case the 3D IC structure comprises a higher number ofvertically stacked semiconductor chips sharing a same internal supplybus, each semiconductor chip may be advantageously provided with arespective communication unit coupled with the internal supply bus. Inthis way, the test stimuli and the test response signals may be encodedand modulated for being transmitted over the internal supply voltage, insuch a way to allow the number reduction of probes necessary to performthe testing on the semiconductor chips forming the stack.

If the semiconductor chip 906 of the top device level has a size smallerthan the size of the semiconductor chip 912 belonging to the adjacent(lower) device level, portions of the top surface 914 of thesemiconductor chip 912 may result not to be covered by the semiconductorchip 906. In this way, the semiconductor chip 912 may be provided withcontact pads on said uncovered portions of its top surface 914, whichcan be directly accessed by probes of the probe card 125 during thetesting. However, even in this case, the number of probes of the probecard 125 necessary for performing the testing may be reduced byimplementing a communication unit coupled with the supply bus in atleast one among the semiconductor chips 906 and 912, in the same ways aspreviously described.

A quite different scenario of application of the concepts of the presentinvention is illustrated in FIG. 9D. Particularly, in the scenarioillustrated in FIG. 9D, the supply voltages VCCA, VCCB required foroperating the integrated circuits ICA and ICB of the 3D IC structure 904have different values, but the 3D IC structure 904 is provided with asingle supply bus 942 only, and particularly including a singlereference voltage line 943 and a single supply voltage line 944. In thesame way as previously described, the supply voltage VCCA (which issubstantially constant) superimposed with encoded and modulated (at apredetermined modulation frequency) test signals generated by the probecard 125 are conveyed over the supply voltage line 944.

The semiconductor chip 906 includes a filter circuit 945 connected tothe supply voltage line 944 for receiving the supply voltage VCCA mixedwith the encoded and modulated test signals. The filter circuit 945separates the constant component (corresponding to the supply voltageVCCA) from the component oscillating at the predetermined modulationfrequency (corresponding to the encoded and modulated test signals). Theconstant component is thus provided to the integrated circuit ICA—whichis also coupled with the reference voltage line 943 for receiving thereference voltage GND—and to a voltage converter circuit 946, such as aDC/DC converter.

The voltage converter circuit 946 converts the constant componentreceived from the filter which corresponds to the supply voltage VCCAinto the supply voltage VCCB for the integrated circuit ICB. Accordingto an embodiment of the present invention, the semiconductor chip 906further includes a mixer circuit 947 having a first input coupled withthe filter circuit 945 for receiving the component oscillating at thepredetermined modulation frequency and corresponding to the encoded andmodulated test signals generated by the probe card 125, and a secondinput coupled with the converter circuit 946 for receiving the supplyvoltage VCCB. The mixer circuit 947 mixes the component oscillating atthe predetermined modulation frequency with the (substantially constant)supply voltage VCCB, conveying the resulting signal to the semiconductorchip 912, for being separated, demodulated and decoded by a propercommunication unit, in the same way as previously described in referenceto the FIGS. 9A-9C. In this way, with the proposed solution it ispossible to further reduce the number of probes required for testing a3D IC structure that has to be supplied with different supply voltages.

According to a still further embodiment of the present invention, thesupply voltage VCCB for the integrated circuit ICB may be supplied onthe supply bus 942 by means of an alternating voltage having anoscillating frequency fp that is different than the ones used forconveying the encoded and modulated test signals. In this case, theconverter circuit 946 will be an AC/DC converter, which converts thealternating voltage into the (constant) supply voltage VCCB, and thefilter circuit 945 will be capable of separating the component of thesignal conveyed by the supply bus 942 that oscillates at the frequencyfp from the components oscillating at the frequencies corresponding tothe encoded and modulated test signals.

In order to satisfy contingent and specific requirements, a personskilled in the art may apply to the solution described above manymodifications and alterations. Particularly, although the presentinvention has been described with reference to preferred embodimentsthereof, it should be understood that various omissions, substitutionsand changes in the form and details as well as other embodiments arepossible; moreover, it is expressly intended that specific elementsand/or method steps described in connection with any disclosedembodiment of the invention may be incorporated in any other embodimentas a general matter of design choice.

Although in the foregoing reference has been made to the use of afrequency-division multiplexing scheme, this is not to be considered aslimitative for the present invention: any technique adapted mixdifferent signal components so as to obtain a combined signal, allowingfor a signal demixing in order to separate the different signalcomponents can be used; similarly, any technique adapted to allowbidirectional communication over a same communication channel can beused (e.g. time-division multiplex).

Moreover, the proposed communication units may be also exploited forperforming the final test of a chip included in a package, a Wafer LevelBurn In (WLBI) test, an on-line test, or a final application test.

Having thus described at least one illustrative embodiment of theinvention, various alterations, modifications, and improvements willreadily occur to those skilled in the art. Such alterations,modifications, and improvements are intended to be within the spirit andscope of the invention. Accordingly, the foregoing description is by wayof example only and is not intended as limiting. The invention islimited only as defined in the following claims and the equivalentsthereto.

What is claimed is:
 1. A test equipment for testing integrated circuits, comprising: a first probe adapted to contact a corresponding first contact terminal of an integrated circuit under test for establishing a first physical communication channel between the test equipment and the integrated circuit under test; a testing circuit electrically connected to said first probe and comprising: a transmitter circuit configured to simultaneously send to the integrated circuit under test, through the first probe and over said first physical communication channel, two test input stimuli signals using two carrier waves at different frequencies that are respectively modulated by the two test input stimuli signals; and a receiver circuit configured to receive from the integrated circuit under test two test response signals using two further carrier waves at different frequencies modulated by the two test response signals.
 2. The test equipment of claim 1, wherein the two test response signals are received from the integrated circuit under test over either said first physical communication channel or a second physical communication channel different from the first physical communication channel; said receiver circuit comprising means for extracting the two test response signals from the modulated two further carrier waves; and the testing circuit further comprising means for assessing a proper functionality of the integrated circuit based on the extracted two test response signals.
 3. The test equipment of claim 2, wherein the two further carrier waves modulated by the two test response signals are received from the integrated circuit under test over said first physical communication channel.
 4. The test equipment of claim 2, wherein said second physical communication channel comprises a second probe, distinct from said first probe, adapted to contact a corresponding second contact terminal of the integrated circuit under test.
 5. The test equipment of claim 1, comprising: means for supplying to the integrated circuit under test at least one power supply.
 6. The test equipment of claim 5, wherein said means for supplying comprises a circuit configured to supply the power supply through said first probe combined with said two carrier waves modulated by the two test input stimuli signals.
 7. The test equipment of claim 5, wherein said means for supplying the power supply comprises a second probe adapted to contact a corresponding power supply contact terminal of the integrated circuit under test to supply a first polarity of the power supply through said second probe.
 8. The test equipment of claim 7, wherein said means for supplying the power supply further comprises a third probe adapted to contact a corresponding power supply contact terminal of the integrated circuit under test to supply a second polarity of the power supply to the integrated circuit under test.
 9. The test equipment of claim 1, wherein the integrated circuit under test comprises: at least one integrated circuit core with said contact terminal adapted to be contacted by said first probe; a built-in self-test circuit coupled to said at least one integrated circuit core and configured to perform a test based on the test input stimuli signals received from the test equipment.
 10. The test equipment of claim 1, wherein said integrated circuit under test comprises: means for receiving the two carrier waves modulated by the two test input stimuli signals; means for extracting the two test input stimuli signals from the modulated two carrier waves; and means for transmitting the two test response signals using the two further carrier waves modulated by the two test response signals.
 11. The test equipment of claim 6, wherein said integrated circuit under test comprises: means for separating the power supply from the first physical communication channel.
 12. The test equipment of claim 1, wherein the integrated circuit under test comprises: a three dimensional integrated circuit structure comprising a sequence of stacked semiconductor chips starting from a bottom semiconductor chip and ending at a top semiconductor chip, each semiconductor chip comprising at least one respective integrated circuit, wherein the first probe is adapted to contact the corresponding first contact terminal located on one of the top or bottom semiconductor chips.
 13. An apparatus, comprising: a test equipment; an integrated circuit under test; wherein the test equipment comprises: at least a first probe configured to contact a corresponding physical contact terminal of the integrated circuit under test and form a first physical communication channel; and a first circuit configured to simultaneously transmit first and second test input stimulus signals through the first probe and over the first physical communications channel to the integrated circuit under test using first and second carrier waves modulated by the first and second test input stimulus signals; and wherein the integrated circuit under test comprises: a second circuit configured to perform a test based on the first and second test input stimulus signals received from the test equipment; and a third circuit responsive to a result of the test performed by the second circuit and configured to transmit a response signal with said result of performing said test over the first physical communication channel and through the first probe to said test equipment using at least a third carrier wave modulated by said first response signal.
 14. The apparatus of claim 13, wherein the integrated circuit under test comprises a three dimensional integrated circuit structure comprising a sequence of stacked semiconductor chips starting from a bottom semiconductor chip and ending at a top semiconductor chip, each semiconductor chip comprising at least one respective integrated circuit, and wherein said physical contact terminal is positioned on one of the bottom or top semiconductor chips.
 15. The apparatus of claim 14, wherein the three-dimensional integrated circuit structure comprises at least one conductive through via crossing the semiconductor chips.
 16. The apparatus of claim 13, wherein the first circuit transmits the first and second test input stimulus signals over the first physical communication channel using the modulated first and second carrier waves at a first frequency and a second frequency, respectively; and wherein the third circuit transmits the first response signal over said first physical communication channel using the modulated second carrier wave at a third frequency.
 17. The apparatus of claim 16, wherein said third frequency is different from the first frequency.
 18. The apparatus of claim 16, wherein the test circuit further comprises: means for extracting the test response signal from the modulated third carrier wave at the third frequency; and means for assessing a proper functionality of the integrated circuit under test based on the extracted test response signal.
 19. The apparatus of claim 13, wherein the test equipment further comprises: a second probe configured to contact a corresponding physical contact terminal of the integrated circuit under test and form a second physical communication channel; and a fourth circuit configured to transmit a second test input stimulus signal over the second physical communications channel to the integrated circuit under test.
 20. The apparatus of claim 13, wherein the test equipment further comprises means for supplying power to the integrated circuit under test.
 21. The apparatus of claim 20, wherein said means for supplying power comprises means for transmitting power with the first and second test input stimulus signals over the first physical communication channel.
 22. The apparatus of claim 21, wherein the integrated circuit under test comprises means for separating the test input stimulus from the transmitted supply of power and using the separated supply of power for powering circuitry of the integrated circuit under test.
 23. The apparatus of claim 21, wherein the means for transmitting power comprises: a power supply; a voltage converter circuit operating responsive to said power supply to generate power; and a circuit configured to provide said power over the first physical communication channel. 